Electronic circuits commonly transmit data signals over relatively long datapaths. However, the signal may be corrupted by RC losses and noises incurred while the signal propagates along the datapath. To facilitate accurate transmission and increase sensitivity to low-level signals, the signal may be implemented as a differential signal. Further, sense amplifier stages may be inserted in the datapath at intervals to restore the. signal to full rail voltage levels. For example, a memory circuit may include differential datapaths from the memory cells to the output buffers, with sense amplifier stages at various points of the datapath.
The datapath can be bi-directional. For example, in some memory circuits, a memory cell is read and written using the same datapath. In these types of circuits, the conventional approach is to use a sense amplifier for each direction; i.e., as used herein, such a conventional sense amplifier stage for a bi-directional datapath has two sense amplifiers, one for each direction. FIG. 1 illustrates part of a memory circuit 10 using such a conventional approach. Memory circuit 10 includes a datapath implemented with datalines DLB and DL. The sense amplifier stage has a read mode sense amplifier 11.sub.1 and a write mode sense amplifier 11.sub.2. The read mode sense amplifier 11.sub.1 is connected to datalines DLB and DL at nodes N11B.sub.1 and N11.sub.1, respectively. As is common in certain types of memory devices, a passgate 12 is connected between datalines DLB and DL at nodes N12B and N12.
In preparation to a memory read operation, passgate 12 is controlled by signal EQUALIZE to provide a conductive path between datalines DLB and DL to equalize the dataline voltage. Memory circuit 10 also includes passgates 18.sub.1, 18.sub.2 and 18.sub.3, which form a precharge circuit. Passgates 18.sub.1, 18.sub.2 and 18.sub.3 are controlled by a signal PRECHB1, which is asserted to provide conductive paths between sense amplifier nodes N11B.sub.2, N11.sub.2, and a supply voltage line providing power supply voltage Vdd. Nodes N11B.sub.2, N11.sub.2 are electrically connected to nodes N12B and N12. Between each data transfer, signal EQUALIZE is asserted to turn on pass gate 12 to cause the voltages on datalines DLB and DL to be at substantially the same voltage level. When signal EQUALIZE is asserted while signal PRECUB1 is asserted, datalines DLB and DL are precharged to a level substantially equal to the level of supply voltage Vdd.
Memory circuit 10 also includes passgates 13.sub.1 and 13.sub.2, inserted in the datapath between the memory cell (not shown) and sense amplifier 11.sub.1. Passgates 13.sub.1 and 13.sub.2 are controlled by a signal DATA_EN to selectively allow a data signal from the memory cell to propagate to sense amplifier 11.sub.1 (e.g., in a read operation). When the data signal from the memory cell is propagated to sense amplifier nodes N11B.sub.1 and N11.sub.1, signal DATA_EN turns off passgates 13.sub.1 and 13.sub.2, and isolates sense amplifier 11.sub.1 from the wire capacitance of datalines DLB and DL. In addition, passgates 13.sub.1 and 13.sub.2 when turned off "store" the differential signals in the parasitic capacitance at nodes N11B.sub.1 and N11.sub.1. Now signal SAE1 is ready to strobe sense amplifier 11.sub.1 to amplify the data signals in nodes N11B.sub.1 and N11.sub.1. Signal READ enables tristate or three-state buffer 14.sub.1 and 14.sub.2 to drive the data signal to the next stage in the datapath after signal SAE1 strobes sense amplifier 11.sub.1. In particular, signal READ is provided so as to keep tristate buffer 14.sub.1 and 14.sub.2 in a high impedance mode before the signals are amplified to avoid large crow-bar current.
This datapath also includes passgates 15.sub.1 and 15.sub.2 connected between the datalines DLB and DL and a write sense amplifier 11.sub.2, respectively. More specifically, passgates 15.sub.1 and 15.sub.2 are connected to nodes N14B and N14 of datalines DLB and DL, and to nodes N15B and N15 of the input leads of sense amplifier 11.sub.2, respectively. Passgates 15.sub.1 and 15.sub.2 are turned on and off by signals WRITE_EN. Memory circuit 10 also includes passgates 18.sub.4, 18.sub.5 and 18.sub.6, which are controlled by a signal PRECHB2 to provide conductive paths between sense amplifier nodes N15B, N15, and power supply Vdd. Between each data transfer, signal PRECHB2 is asserted to turn on passgates 18.sub.4, 18.sub.5 and 18.sub.6 to electrically connect and precharge nodes N15B and N15 to a level substantially equal to the level of voltage Vdd.
Memory circuit 10 also includes passgates 17.sub.1 and 17.sub.2, which are connected between the output leads of inverters N15B and N15 and nodes N13B and N13 of datalines DLB and DL, respectively. Passgates 17.sub.1 and 17.sub.2 are controlled by signal WRITE. Nodes N13B and N13 are located between the memory cell (not shown) and passgates 13.sub.1 and 13.sub.2. During read operations, signal WRITE_EN, and signals WRITE are provided so as to disable passgates 15.sub.1 and 15.sub.2, and passgates 17.sub.1 and 17.sub.2, respectively. Thus, sense amplifier 11.sub.2 has no significant affect on datalines DLB and DL during a read operation.
In contrast, during a write operation, signal SAE1 does not strobe. Thus, sense amplifier 11.sub.1 does not affect the voltage on datalines DLB and DL during a write operation. In addition, during a write operation, signals WRITE_EN is provided so as to turn on pass gates 15.sub.1 and 15.sub.2, which allows sense amplifier 11.sub.2 to amplify the data signal on datalines DLB and DL. Signals WRITE is also provided to turn on passgates 17.sub.1 and 17.sub.2 to allow the amplified data signal to be driven by sense amplifier 11.sub.1 to nodes N13B and N13 of the datalines.
FIG. 2 shows the timing and the waveforms of the control signals for a write operation in memory circuit 10 (FIG. 1). As indicated by the dashed lines, there are several setup time requirements in this conventional memory circuit. For example, there is a setup time required from: (a) the rising edge of signal PRECHB2 to the rising edge of signal WRITE_EN, indicated as (t2-t1); (b) the falling edge of signal WRITE_EN to the rising edge of signal SAE2/falling edge of signal EQUALIZE, indicated by (t4-t3); (c) from the rising edge of signal SAE2 to the rising edge of signal WRITE, indicated by (t5-t4); (d) from the falling edge of signal WRITE to the falling edge of signal SAE2, indicated by (t7-t6); and (e) from the falling edge of signal SAE2 to the falling edge of signal PRECHB2, indicated by (t8-t7). These setup times need to be equal to or greater than zero to assure that the data signals are sensed and amplified properly, and driven along datalines DLB and DL in the right directions.
FIG. 3 shows the timing and the waveforms of the control signals for a read operation in memory circuit 10 (FIG. 1). As can be seen, there is also a set of setup times to meet as in a write operation. The setup times depend on the skews between the control signals. The greater the skews in the control signals, the greater the setup times need to be. If there are no skew between the control signals, the setup times can become zero. However, the control signals are typically global signals, which tend to have high skew compared with locally generated signals. The reason why the control signals are globally generated is that each signal has different pulse width and delay requirements as shown in FIGS. 2 and 3. The pulse-width modifying and delay adjustment circuits would make the chip very bulky and power consuming if implemented in the local area near each sense amplifier stage. Because of the global skews, the percentage of the useful cycle time is reduced and the frequency at which the data can be transferred decreases.
As can be seen, another problem with this approach is that it requires two sense amplifiers for each sense amplifier stage (i.e., sense amplifiers 11.sub.1 and 11.sub.2). This can result in a significant amount of area occupied by sense amplifiers in a memory circuit with a large number of memory cells and/or datapaths that require a relatively large number of sense amplifier stages. Moreover, using two sense amplifiers requires two sets of passgate control, sense amplifier enabling and precharge/equalize signals. This means that twice as many wires are needed for control, thereby further increasing the size of the memory circuit. Furthermore, when the operation is reversed from read to write, for example, the control signals cannot be symmetrically switched. That is, signal SAE2 cannot simple be switched to signal SAE1, nor signal PRECHB2 to signal PRECHB1, nor signal WRITE to signal READ, and so on. More specifically, the clock edge at which data are required to be available at the input buffers of the memory system in a write cycle is typically the same clock edge at which the data are made ready at the output buffers of the memory system in a read cycle. This constraint causes the data to appear at nodes N14B and N14 at the same time in read and in write operations, but appear at nodes N12B and N12 earlier in read operations and later in write operations. Therefore, there are also extra delays and multiplexing for the bi-directional operations.
The delay, pulse width modification and multiplexing circuitry required to achieve this timing increases the complexity, size, design costs, and fabrication cost of the circuit. Moreover, implementing the control signals globally to alleviate power and area penalty dramatically increases the skew of the control signals, which in turn degrades the performance the memory circuit can achieve. Still further, the requirement of a precharge phase during each data transfer undesirably increases the cycle time of the transfer. Accordingly, there is a need for an approach that reduces the complexity and size of a sense amplifier stage and its corresponding control circuitry while minimizing the cycle time.